1. Technical Field
The present invention relates generally to Integrated Circuit (IC) memory devices and more specifically to sense amplifier control of synchronous and asynchronous memory devices.
2. Discussion of the Prior Art
On both synchronous and asynchronous IC memory devices, such as SRAM (Static Random Access Memory) devices, dynamic, clocked sense amplifiers are used. Clocked sense amplifiers provide the advantage that they consume no DC current and thus the power consumed by the IC memory device is kept to a minimum. While sense amplifier circuitry has attractive power consumption characteristics, it is incapable of recovering from an initial false sensing and therefore must not be clocked too early. False sensing is usually prevented by designing in signal margin for the sense amplifier circuitry of the memory device. The sense amplifier signal margin determines the amount of differential signal input to the sense amplifier that is allowed to develop before the sense amplifier is clocked. The sense amplifier signal margin of the memory device prevents false sensing of the device.
The sense amplifier signal margin of a memory device is commonly defined internal to the memory device. During the design phase of the memory device, a suitable sense amplifier signal margin is selected. Since the sense amplifier signal margin of a memory device is clocked internal to the memory device, it is not subject to external control or modification.
While internally controlled clocking of the sense amplifier circuitry ensures that the selected sense amplifier signal margin of the memory device is not violated, it does not, of course, allow for flexibility as to when the sense amplifier circuitry is clocked. There are advantages to be gained from being able to selectively clock the sense amplifier circuitry of a memory device. More aggressive device timings could be emulated and a faster or a slower setting of the memory device could be accordingly set. This could be accomplished by appropriate exercise of a fuse option, for instance. Also, selective clocking of the sense amplifier circuitry could be used as a stress test to identify weak bits that could then be repaired through the use of redundant elements. Additionally, selective clocking could be employed to determine the performance limits of a device.
Internally controlled clocking of the sense amplifier circuitry of a memory device does not allow these advantages to be realized. There is therefore a need in the art to be able to externally control the clocking of sense amplifiers of a memory device, external to the memory device.